cisco systemsSan Jose, CA
Advanced Packaging Design Engineering Team Lead (Hybrid)
Advanced Packaging Design Engineering Team Lead (Hybrid)
Semiconductor and Related Device ManufacturingSemiconductor Machinery ManufacturingOther Electronic Component Manufacturing
Apply for this role (opens in a new tab)Overview:
In this role you drive the San Jose package design program within Cisco Silicon One, shaping high-performance ASIC packaging for global networks. You lead and mentor a cross-functional team, partnering with layout, SI/PI, silicon architecture, and manufacturing to deliver robust, scalable package solutions. You influence design methodologies and development flows to improve quality and efficiency while advancing next-gen ASIC platforms. This is a hands-on leadership role at the intersection of engineering excellence and team growth, with a clear impact on product performance and delivery. Compensation / Benefits Medical, dental, and vision insurance 401(k) with Cisco matching Paid parental leave Disability coverage (short and long-term) Basic life insurance Restricted stock units (RSUs)
Responsibilities:
Lead complex package design programs from concept to tapeout Optimize pinouts, stack-ups, PDN and high-speed routing balancing performance and manufacturability Collaborate with silicon floor planning, SI/PI to ensure system-level alignment Work with layout editors and implementation teams to deliver quality package layouts Mentor and grow the San Jose package design team, fostering ownership of complex programs Coordinate resources across designers, layout editors, and contractors Enhance packaging methodologies and partner with vendors to improve quality and efficiency Drive innovation in package solutions for Cisco’s next-generation ASIC platforms
Key requirements:
Bachelor’s degree in Electrical Engineering or related field with 8+ years of relevant experience or Master’s degree with 6+ years Experience in high-speed package design including SI considerations and PDN Experience with industry-standard EDA tools for package layout and design Experience with technical leadership in complex hardware or silicon development programs Leadership and mentoring Cross-functional collaboration Accountability and continuous improvement High-speed package design Signal integrity (SI) considerations Power integrity (PI) and PDN design
Also on the board Same function, level within a rung
Level
Lead
Location
San Jose, CA
Occupation
Electronics Engineers, Except Computer
Industry
Semiconductor and Related Device Manufacturing
Posted
today