cisco systemsSan Jose, CA
Memory Semiconductor Component Engineering Technical Leader Hybrid
Memory Semiconductor Component Engineering Technical Leader Hybrid
Computer Systems Engineers/ArchitectsElectronics Engineers, Except ComputerComputer Hardware Engineers
Semiconductor and Related Device ManufacturingOther Electronic Component ManufacturingElectronic Computer Manufacturing
Apply for this role (opens in a new tab)Overview:
In this role you will serve as Cisco’s domain expert for memory technologies, guiding selection, validation, and qualification of memory components for Cisco products. You will influence vendor roadmaps and support design teams to integrate next-gen memory into our platforms. You’ll lead investigations into memory solutions and work with vendors to drive corrective actions. This role sits at the intersection of design, manufacturing, and quality engineering, shaping memory reliability across Cisco products. Compensation / Benefits medical, dental, and vision insurance 401(k) with Cisco matching paid parental leave paid vacation and flexible time off options sick time with carryover volunteer days
Responsibilities:
Collaborate with design teams to enhance memory quality and reliability across Cisco platforms Serve as SME for memory technologies, advising on next-generation solutions Assess emerging memory tech, architectures, and roadmaps for feasibility and readiness Lead investigations and end-to-end failure analyses with vendors to define corrective actions (8D, RCA) Influence design decisions to ensure memory is integrated into next-generation products
Key requirements:
BS/MS in Electrical Engineering, Computer Engineering, or related fields 8+ years’ memory design/application or Field Application Engineering experience Knowledge of DDR6 and evolving JEDEC memory standards and their impact on product readiness Strong understanding of DRAM ECC methodologies (Partial Chipkill, SDDC) to enhance reliability Comprehensive knowledge of DRAM technologies (DDRx, LPDDRx, HBM) and their server/network applications Strong problem-solving skills Effective conflict resolution abilities DDR6 and JEDEC memory standards DRAM ECC methodologies (PCLS, SDDC) DRAM technologies (DDRx, LPDDRx, HBM) memory technology assessment and qualification
Also on the board Same function, level within a rung
Level
Lead
Location
San Jose, CA
Occupation
Computer Systems Engineers/Architects
Industry
Semiconductor and Related Device Manufacturing
Posted
today