Staff Engineer, SRAM Circuit Design

Responsibilities: Design and develop SRAM memory arrays (bit cells, sense amps, decoders, control circuits) for advanced nodes Optimize SRAM for performance, power and area, and improve yield Create custom layouts and perform physical design verifications (DRC, LVS) Assess speed-power-area trade-offs to meet targets Develop and improve design methodologies including automation scripts for design, simulation, and verification Collaborate with product and test teams to develop test plans and support silicon bring-up Mentor junior engineers on SRAM design techniques Conduct extensive circuit simulations (HSPICE, finesim, Cadence Spectre) to validate functionality and performance Contribute to patents, papers, or industry conference work

Key requirements: Bachelor's or Master in Electrical Engineering with extensive SRAM/memory design experience Proven track record delivering SRAM designs in advanced nodes Strong understanding of semiconductor device physics and process technologies (FinFET, GAA, SOI) Expertise in SRAM architecture (bitcells, sense amps, write/read paths) Experience with timing analysis, power analysis, and DFM Proficiency with circuit simulation tools (Spectre, HSPICE, Cadence Virtuoso) Scripting skills (Python, Perl, TCL) for automation Strong cross-functional collaboration and communication Experience with 5nm/3nm or beyond nodes Knowledge of SRAM compiler development and low-power techniques (power gating, voltage scaling) Background in silicon debug and root-cause analysis Inclusive, learner, collaborative, innovative mindset collaboration clear communication problem-solving mindset SRAM architecture and design (bitcells, sense amps, write/read paths) Advanced process nodes (2nm–5nm) Circuit simulation (HSPICE, Cadence Spectre, finesim)