astera labsSan Jose, CA
VP, Physical Design & Chiplet Architecture
VP, Physical Design & Chiplet Architecture
VP, Physical Design & Chiplet Architecture
astera labsSan Jose, CA
yesterday
Computer Hardware EngineersElectronics Engineers, Except ComputerArchitectural and Engineering Managers
Semiconductor and Related Device ManufacturingResearch and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)Other Electronic Component Manufacturing
Apply for this role →Astera Labs seeks a VP of Physical Design to lead full-chip physical design for next-generation switching products with UCIe and UALink. You will drive multi-die architectures, tapeouts, and performance targets in collaboration with architecture, digital design, packaging, and silicon teams.
You will mentor a growing PD team, ensure robust timing closure, power and area optimization, and lead efforts across 7nm or below node implementations.
Also on the board Same function, level within a rung
Level
Manager
Location
San Jose, CA
Occupation
Computer Hardware Engineers
Industry
Semiconductor and Related Device Manufacturing
Posted
yesterday