Design Verification Engineers (Sunnyvale, CA)

Locations Sunnyvale, CA Job Fields Testing & DV We are looking for talented Verification Engineers to expand our International Design Verification team. Qualifications Bachelor’s or Master’s in Electrical or Computer Science 4 years of Design Verification experience Very good understanding of Design Verification goals and challenges Ability to adapt to a start-up fast paced dynamic environment Excellent communication skills Very good knowledge of SystemVerilog and UVM Ability to find what can go wrong when everybody else feels safe Candidates should be able to demonstrate skills, knowledge and experience on a reasonable subset of the following: Verification environments architecture and implementation Verification tools architecture and implementation Processors architecture with understanding of execution pipelines GPUs or vector processing engines architecture Cache hierarchy and MMU architecture Cache coherency protocols Standard protocols like PCIe and DDR4/5 Regression infrastructure architecture and implementation Verification process and test plan development Assertion-based verification using SVA/OVA Functional coverage methodology and implementation Formal equivalence checking tools like Jasper Theorem provers like ACL2 Experience Debugging complex test scenarios Working on FPGA emulated platforms Working in a Linux environment Using git version control system Using a scripting language (Perl or Python) Using C programming language Using C++ programming language Using TCL and Expect