osi engineeringSan Jose, CA
Hybrid Principal Verification Engineer Lead Full-Chip UVM
$170,000 – $196,000
Apply →Hybrid Principal Verification Engineer Lead Full-Chip UVM
Hybrid Principal Verification Engineer Lead Full-Chip UVM
osi engineeringSan Jose, CA
10 days ago
$170,000 – $196,000
Semiconductor and Related Device ManufacturingPrinted Circuit Assembly (Electronic Assembly) ManufacturingOther Electronic Component Manufacturing
Apply for this role →A leading chip and silicon IP provider is seeking a Principal Verification Engineer in San Jose, CA. This full-time hybrid role involves leading verification strategies and working alongside talented engineers. Candidates should have extensive experience in SystemVerilog and UVM, with a strong background in ASIC verification tools. The position offers a salary range of $170,000 – $196,000 based on experience.
Also on the board Same function, level within a rung
Level
Lead
Salary
$170,000 – $196,000
Location
San Jose, CA
Occupation
Computer Hardware Engineers
Industry
Semiconductor and Related Device Manufacturing
Posted
10 days ago