Media Tek Research Lab Inc. in San Jose seeks a senior memory design engineer to define and design custom memory blocks (SRAM/TCAM) for Cloud AI and data center ASICs. You will collaborate with product and architecture teams, mentor layout engineers, and drive DV plans across global CAD teams. The ideal candidate has 10+ years in embedded memory design, a PhD or MS in EE, experience with Prime Time/Nanotime, and scripting in Perl/Python.

Also on the board Same function, level within a rung

Level

Lead

Location

San Jose, CA

Occupation

Computer Hardware Engineers

Industry

Semiconductor and Related Device Manufacturing

Posted

yesterday

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