Lead Design Verification

Responsibilities: Develop verification methodology and testbenches for digital and mixed-signal blocks. Design test plans, conduct coverage analysis, and ensure closure for parallel link and Ser Des IP blocks, as well as on-chip interconnects.

Basic Qualifications: BSc or MSc in Electrical Engineering, Computer Engineering, or related fields.

Experience: US-based lead should have 10+ years of ASIC design verification experience. Other engineers should have 2-5 years of work or academic experience in ASIC design verification. Proven ability to handle various technical tasks independently and complete projects. Proficient in System Verilog and UVM testbench development for complex digital and PHY blocks, including AMS and WREAL modeling. Skilled in pre-synthesis and post-place-and-route functional verification using tools like NCSIM, VCS, Model Sim. Programming or scripting experience. Experience with version control software such as Git.

Preferred Qualifications: Experience with digital designs involving multiple clock domains and clock dividers. Verification experience with Ser Des IP interfaces in complex SoC environments. Knowledge of verification for PCS, PMA Ser Des layers, and internal Ser Des digital backends. Experience with HBM memory interface verification (PHY and controller). Familiarity with formal model equivalence checking tools and methodologies. Programming experience in Python is a plus.

Seniority Level: Mid-Senior level

Employment Type: Full-time

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