Roguebeam is seeking a Senior Physical Design Engineer to own block- and chip-level implementation from netlist to GDS, with FPGA P&R support, for phased-array solutions. You will floorplan, place, clock, route, and sign off silicon that carries digital beamforming and adaptive processing. You will collaborate end-to-end on timing, CTS, and verification, integrating memories, high-speed interfaces, and DFT structures.

Also on the board Same function, level within a rung

Level

Lead

Location

Seattle, WA

Occupation

Computer Hardware Engineers

Industry

Semiconductor and Related Device Manufacturing

Posted

yesterday

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