Senior Verification Lead – ASIC/FPGA (Remote)

Fidus is seeking a Verification Designer to lead block- and system-level verification for ASIC/FPGA designs. You will build UVM, formal, and assertion-based verification environments, drive coverage closure, and own verification strategy across diverse domains. You’ll work with clients directly and travel as needed. The role requires 8+ years in ASIC/FPGA verification, strong SystemVerilog/UVM skills, and experience with CRV and coverage metrics. A related degree is required.