Proxelera PVT LTD is seeking a Physical Design Engineer with strong expertise in Place & Route (PnR), PPA optimization, and timing convergence for advanced technology nodes. You will drive block-level physical design from netlist to GDSII and collaborate with RTL/DFT/STA teams to ensure successful tapeouts. The role requires experience in floorplanning, CTS, timing closure, EMIR analysis, and signoff methodologies.

Also on the board Same function, level within a rung

Level

Senior

Location

Austin, TX

Occupation

Electronics Engineers, Except Computer

Industry

Printed Circuit Assembly (Electronic Assembly) Manufacturing

Posted

yesterday

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