Senior ASIC / SoC Network-on-Chip Design Engineer

Experience: -Job Type: Full Time

Location: Mountain View, CA

Location: Mountain View CA (onsite - Hybrid)

Job Type: Full Time.

Responsibilities: Design high-performance, high-bandwidth Network-on-Chip (NoC) IP for advanced AI SoCs. Define microarchitecture specifications and develop synthesizable RTL using Verilog/System Verilog. Drive synthesis, timing constraints, CDC/Lint closure, and PPA optimization. Integrate IP across SoC subsystems and support post-silicon debug. Collaborate with architecture, verification, physical design, and SoC integration teams. Develop Python scripts for design automation and productivity.

Qualifications: 8+ years delivering ASIC/SoC IP designs.6+ years of hands-on digital design, RTL, and microarchitecture experience. Strong experience with Verilog/System Verilog, synthesis, timing constraints, CDC, Lint, and PPA trade-offs. Experience with NoC/interconnect and high-throughput/low-latency designs. Experience with SoC integration, post-silicon debug, and Python scripting.

Key Skills: ASIC | NoC | RTL | System Verilog | Microarchitecture | CDC | Lint | Synthesis | Timing | PPA | Python