astera labsSan Jose, CA
Principal SerDes/PHY Verification Lead
Principal SerDes/PHY Verification Lead
Principal SerDes/PHY Verification Lead
astera labsSan Jose, CA
9 days ago
Semiconductor and Related Device ManufacturingResearch and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)Electronic Computer Manufacturing
Apply for this role →Astera Labs is hiring a Principal Design Verification Engineer to own the functional verification of our high-speed Ser Des/PHY IP—the connectivity engine powering rack-scale AI infrastructure. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success at the analog/digital boundary.
You will partner with PHY analog/mixed-signal designers, digital architects, and SoC integration teams to verify multi-Gbps Ser Des blocks used in PCIe Gen 6/Gen 7,
Also on the board Same function, level within a rung
Level
Lead
Location
San Jose, CA
Occupation
Computer Hardware Engineers
Industry
Semiconductor and Related Device Manufacturing
Posted
9 days ago