Tektronix is seeking an experienced ASIC Layout Design Engineer to perform block and chip-level layout of high-performance RF analog ASICs, collaborating with design engineers and layout teams. You will ensure smooth product flow from development to mass production, driving yield and test-time improvements. The role requires 7+ years in RF/Analog/Mixed-Signal layout, proficiency with Cadence Virtuoso and PDKs across multiple foundries, and strong skills in layout planning, routing, and

Also on the board Same function, level within a rung

Level

Lead

Location

Boulder, CO

Occupation

Electronics Engineers, Except Computer

Industry

Semiconductor and Related Device Manufacturing

Posted

4 days ago

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