NVIDIA Corporation is seeking a Senior Signal Integrity Engineer to design and optimize high-frequency channels up to 400 Gb/s per lane for PCBs, packages, connectors and cables. You will establish layout guidelines for NVIDIA systems and work on both design and verification to ensure robust PHY performance. The role requires deep EM knowledge, hands-on lab experience with VNA and TDR, and proficiency with tools like Ansys EM and CST.

Also on the board Same function, level within a rung

Level

Lead

Location

Santa Clara, CA

Occupation

Computer Hardware Engineers

Industry

Other Electronic Component Manufacturing

Posted

yesterday

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Senior SI Engineer 400Gb/s PHY Design (Equity) at nvidia | Johnson...