JRC Integrated Systems seeks a Senior Standard Cell Design Engineer to lead Radiation Hardened LEAP library development and collaborate with foundries on MPW runs. You will shape simulation tools for reliability prediction and drive PPA optimization for extreme environments. You have deep semiconductor design experience, hands-on standard cell and layout skills, and familiarity with Virtuoso/Spectre/HSPICE. Eligibility for a U.S. security clearance is required.

Also on the board Same function, level within a rung

Level

Lead

Location

Saint Paul, MN

Occupation

Electronics Engineers, Except Computer

Industry

Semiconductor and Related Device Manufacturing

Posted

today

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