Lead Physical Design Engineer - Timing, CTS/STA Expert

Digicomm Semiconductor INC in the United States is seeking a physical design engineer to analyze circuits, partition designs into blocks, and place blocks efficiently across the chip area. The role includes allocating space for external hard IPs and performing PPO before CTS to optimize timing paths. The position covers clock routing to minimize skew, CTS execution, end-to-end STA timing checks, constraint budgeting, and timing sign-off.