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Broadcom is seeking a senior physical design engineer in the Irvine/San Jose area to drive the implementation of complex chips from netlist to GDSII. You will lead floorplanning, partitioning, and block pin assignments, and perform PnR, timing closure, and verification with strong scripting to automate flows. Experience in low-power IC design and Mentor Calibre for physical verification is highly valued. A bachelor's degree with 8+ years (or a master's with 6+ years) is required, with location

Also on the board Same function, level within a rung

Level

Lead

Location

San Jose, CA

Occupation

Computer Hardware Engineers

Industry

Semiconductor and Related Device Manufacturing

Posted

3 days ago

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