Capgemini Engineering in Santa Clara, CA, is seeking a Senior Physical Design Engineer to drive complex IC implementations at advanced nodes. You will lead floorplanning, placement, clock tree synthesis, routing and power-grid strategies, collaborating across teams to meet timing, power and area goals, and ensure tape-out readiness. The role requires 10+ years in physical design, LVS/DRC debugging, CDC and timing analysis, and hands-on use of Virtuoso, Calibre and similar EDA tools.

Also on the board Same function, level within a rung

Level

Lead

Location

Brooklyn, NY

Occupation

Computer Hardware Engineers

Industry

Semiconductor and Related Device Manufacturing

Posted

today

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