astera labsSan Jose, CA
Tech Lead, AI Connectivity Silicon Design & RTL
Tech Lead, AI Connectivity Silicon Design & RTL
Tech Lead, AI Connectivity Silicon Design & RTL
astera labsSan Jose, CA
yesterday
Architectural and Engineering ManagersComputer Hardware EngineersElectronics Engineers, Except Computer
Semiconductor and Related Device ManufacturingComputer Systems Design ServicesResearch and Development in the Physical, Engineering, and Life Sciences
Apply for this role (opens in a new tab)Astera Labs is seeking a Tech Lead Design Engineer to architect and deliver connectivity silicon powering AI clusters. You will own RTL design for assigned blocks from microarchitecture through synthesis, and drive high-quality design flows. This high-impact role requires collaboration with architecture, verification, DFT, and physical design to move features from spec to silicon and ensure tapeout readiness.
Also on the board Same function, level within a rung
Level
Lead
Location
San Jose, CA
Occupation
Architectural and Engineering Managers
Industry
Semiconductor and Related Device Manufacturing
Posted
yesterday