ASIC Design Architect

Job Title: ASIC Architect / Senior ASIC Architect

Department: Hardware Engineering / Semiconductor Design

Employment Type: Full-Time

Level: Senior / Staff / Principal

Position Summary: We are seeking an experienced and highly motivated ASIC Architect to lead the definition, design, and optimization of complex Application-Specific Integrated Circuits (ASICs) and System-on-Chip (SoC) solutions. The ideal candidate will possess deep expertise in digital hardware architecture, microarchitecture, semiconductor design methodologies, and system-level performance optimization. This individual will be responsible for translating product and system requirements into scalable, power-efficient, high-performance silicon architectures. The ASIC Architect will collaborate closely with system architects, RTL designers, verification engineers, physical design teams, firmware developers, and product engineering teams to deliver innovative semiconductor solutions that meet aggressive performance, power, area (PPA), cost, and schedule objectives. Key Responsibilities1. ASIC and SoC Architecture Development Define and develop ASIC/SoC architectures based on product requirements, application workloads, and system-level specifications. Establish architectural specifications, functional partitioning, block diagrams, and interface definitions. Evaluate architectural trade-offs involving performance, power consumption, silicon area, latency, bandwidth, and implementation complexity. Define microarchitectures for high-performance digital processing blocks, datapaths, control logic, and memory subsystems. Develop scalable architectures supporting multiple product generations and technology nodes.2. Performance, Power, and Area Optimization Drive architectural analysis and optimization to achieve competitive PPA targets. Develop analytical models and simulation environments to evaluate architecture alternatives. Analyze system throughput, latency, memory bandwidth, clock frequencies, and resource utilization. Define power management strategies, including clock gating, power gating, dynamic voltage and frequency scaling (DVFS), and low-power operating modes. Collaborate with physical design engineers to evaluate timing closure, floorplanning, congestion, and implementation feasibility.3. Microarchitecture and RTL Design Translate high-level architectural requirements into detailed microarchitecture specifications. Provide technical direction to RTL design teams implementing Verilog and SystemVerilog designs. Define pipelining, parallel processing, arbitration, buffering, clock-domain crossing, and reset strategies. Review RTL implementations to ensure architectural compliance, efficiency, scalability, and synthesizability. Identify and resolve architectural bottlenecks throughout the design lifecycle.4. System Integration and Interfaces Architect on-chip interconnects, memory hierarchies, DMA engines, and subsystem interfaces. Define integration requirements for processors, accelerators, embedded memories, and third-party IP.Specify and optimize industry-standard interfaces and protocols, including AMBA AXI/AHB/APB, PCIe, DDR, Ethernet, or other application-specific interfaces. Collaborate with firmware and software teams to define hardware/software interfaces, register maps, interrupts, and system initialization sequences.5. Verification, Validation, and Silicon Bring-UpWork with verification teams to establish architecture-level verification strategies and coverage requirements. Define performance validation methodologies and reference models. Support formal verification, simulation, emulation, and FPGA prototyping activities. Participate in design reviews, technical risk assessments, and architecture sign-off. Support post-silicon bring-up, characterization, performance tuning, and root-cause analysis.6. Technical Leadership Serve as a technical authority for ASIC architecture and microarchitecture decisions. Lead architectural reviews and communicate technical trade-offs to engineering leadership. Mentor ASIC designers and junior architects. Collaborate across multidisciplinary engineering teams to resolve complex design challenges. Evaluate emerging semiconductor technologies, design methodologies, and architectural innovations.

Education and Experience: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a closely related discipline.12+ years of relevant experience in ASIC/SoC architecture, digital design, or microarchitecture development. Demonstrated experience architecting and delivering complex ASIC or SoC designs through successful silicon tape-out. Proven ability to lead architectural decisions for large-scale digital semiconductor systems.

Technical Expertise: Strong understanding of digital logic design, computer architecture, and SoC design principles. Extensive knowledge of RTL design using Verilog and SystemVerilog. Expertise in architecture and microarchitecture design, including pipelines, state machines, datapaths, arbitration, and memory systems. Strong understanding of ASIC design flows, including synthesis, static timing analysis (STA), physical design, and design-for-test (DFT).Experience with performance modeling, architecture exploration, and PPA analysis. Understanding of clock-domain crossing (CDC), reset-domain crossing (RDC), timing constraints, and low-power design methodologies. Familiarity with standard on-chip communication protocols such as AXI, AHB, and APB.Proficiency in scripting and modeling languages such as Python, C/C++, Tcl, or MATLAB.Strong analytical, debugging, and problem-solving skills.

Preferred Qualifications: Ph. D. in Electrical Engineering, Computer Engineering, or a related field.12+ years of experience in ASIC/SoC architecture and semiconductor product development. Experience with advanced semiconductor process nodes (7nm, 5nm, 3nm, or comparable technologies).Experience architecting high-performance compute accelerators, AI/ML processors, networking ASICs, storage controllers, or communications SoCs. Knowledge of cache coherency, NoC architectures, memory controllers, and high-bandwidth memory systems. Experience with high-speed interfaces such as PCIe, Ethernet, DDR4/DDR5, LPDDR, or HBM.Experience with power estimation, performance simulation, and architecture modeling tools. Familiarity with functional safety, reliability, security, and hardware protection mechanisms. Experience collaborating with semiconductor foundries, EDA vendors, and third-party IP providers. Experience with multiple successful ASIC tape-outs and post-silicon product launches.