resource logisticsCalifornia, MO
ASIC Physical Design Engineer: Floorplan to Tape-out
ASIC Physical Design Engineer: Floorplan to Tape-out
ASIC Physical Design Engineer: Floorplan to Tape-out
resource logisticsCalifornia, MO
yesterday
Semiconductor and Related Device ManufacturingProcess, Physical Distribution, and Logistics Consulting ServicesResearch and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)
Apply for this role →Resource Logistics Inc. is seeking an experienced ASIC physical design engineer to drive block-level implementation from floorplan to tape-out. You will optimize floorplans, placement, CTS, routing, and ECO activities to meet timing, power, area, and congestion targets.
Collaborate with STA, DFT, and RTL teams while developing automation scripts in TCL, Perl, and Python to boost productivity and ensure sign-off readiness.
Also on the board Same function, level within a rung
Level
Lead
Location
California, MO
Occupation
Electronics Engineers, Except Computer
Industry
Semiconductor and Related Device Manufacturing
Posted
yesterday