annapurna labsSpringfield, IL
Formal Verification Engineer, Annapurna Labs
Formal Verification Engineer, Annapurna Labs
Formal Verification Engineer, Annapurna Labs
annapurna labsSpringfield, IL
Apply for this role (opens in a new tab)2 days ago
Description:
Annapurna Labs, part of AWS, designs the silicon behind AWS infrastructure, including AWS Graviton processors and the AWS Nitro System. What you prove here runs in millions of servers worldwide.
Annapurna Labs, part of AWS, designs the silicon behind AWS infrastructure, including AWS Graviton processors and the AWS Nitro System. What you prove here runs in millions of servers worldwide. Formal verification is everywhere in our projects. Each project has hundreds of formal environments, from small blocks with sophisticated data crunching or complex FSMs up to chip-fabric deadlock verification.
The Role:
As an L5 Formal Verification Engineer, you'll own FV for blocks within a Graviton or Nitro subsystem, end to end from architecture to sign-off. You'll work with technical leads and serve as a mentor and knowledge source for other engineers.
Your Ideas Shape The Team
If a technique works, we adopt it, whoever proposed it. We're pushing AI and agentic flows into everyday verification work, and your ideas will decide how far it goes. Senior engineers on our team are co-inventors on formal verification patents.
What We Offer:
A role we count on: formal results drive sign-off decisions, and other teams plan around them
Involvement from day one: FV engineers join at architecture, define what must be proven, and shape designs to be provable before RTL is written
A real partnership with design: we define verification intent together
A team where senior FV leaders work alongside early-career engineers who bring energy and fresh ideas. We like the work, and we like working together.
Key job responsibilities
Own formal verification of your blocks from architecture through sign-off
Write the formal plan and define what must be proven
Build formal environments covering FPV, sequential equivalence, connectivity, X-prop, security, and liveness
Solve convergence problems with abstraction, invariants, and decomposition
Report clearly what is proven, what is bounded, and what is still open
Work with design teams to define verification intent and improve design quality
Bring new techniques, including AI and agentic flows, into team flows
Basic Qualifications: Bachelor's degree in Electrical Engineering or a related field
Bachelor's degree in Electrical Engineering, Computer Science, or a related field
5+ years of hands-on formal verification experience
Strong knowledge of SystemVerilog Assertions (SVA)
Hands-on experience with industry formal tools (any vendor)
Owned formal closure on complex blocks
Preferred Qualifications: Abstraction and complexity-reduction techniques
Cover-based and semi-formal verification, and helper assertions
Protocol knowledge: APB, AXI, CHI, networking related
Experience or strong interest in applying AI to engineering work
Experience mentoring other engineers
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Company
Annapurna Labs Ltd.
Job ID: A10583059
Also on the board Same function, level within a rung
Level
Lead
Location
Springfield, IL
Occupation
Validation Engineers
Industry
Computer Systems Design Services
Posted
2 days ago