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Overview: In this role you will contribute to the design and analysis of next-generation DDR memory interfaces at data rates above 16 GT/s. You’ll collaborate with SI, PI, package, design, and validation teams to model, analyze, and validate high-speed memory systems, driving measurements from silicon bring-up to lab verification. The work blends simulation, lab diagnostics, and automation to advance Rambus memory products for data-center and AI workloads. This is a hands-on, cross-functional role with a clear impact on system performance and reliability. Compensation / Benefits base salary bonus equity matching 401(k) employee stock purchase plan medical and dental benefits
Responsibilities: Support SI/PI analysis and simulations for memory interface products and package/board designs Assist in channel modeling and simulation of high-speed DDR interfaces Perform SI/PI studies on signal quality, jitter, crosstalk, return loss, eye diagrams, and PDN performance Collaborate with design, package, and validation teams to interpret requirements and results Correlate simulations with oscilloscope, TDR, and VNA measurements Develop simulation methodologies, automation scripts, and analysis flows Document results and present findings to cross-functional teams Participate in silicon bring-up and debugging as needed
Key requirements: MS degree in Electrical Engineering preferred or BS degree with strong academic performance Coursework/research in SI, PI, electromagnetics, high-speed digital design, RF/microwave, or communications Strong understanding of transmission line theory, S-parameters, reflection and termination, crosstalk, and jitter Familiarity with circuit simulation tools such as SPICE, Keysight ADS, HFSS, PowerSI, Ansys EM tools Proficiency in scripting (Python, MATLAB, Tcl) Strong analytical/problem-solving skills; good written/verbal communication; collaborative work style Preferred: DDR interfaces, SerDes, high-speed I/O, package and PCB design experience Experience with ADS, HFSS, Q3D, PowerSI, Cadence Allegro; measurement equipment (oscilloscope, VNA, TDR); knowledge of equalization techniques (FFE, DFE, CTLE) Strong analytical thinking Collaborative teamwork Clear written and verbal communication SPICE Keysight ADS HFSS

Also on the board Same function, level within a rung

Level

Lead

Location

San Jose, CA

Occupation

Electronics Engineers, Except Computer

Industry

Engineering Services

Posted

today

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