Senior SRAM IC Layout Engineer – Advanced CMOS (5nm/3nm)
Senior SRAM IC Layout Engineer – Advanced CMOS (5nm/3nm)
rose internationalSanta Clara, CA
yesterday
Semiconductor and Related Device ManufacturingElectronic Computer ManufacturingSemiconductor Machinery Manufacturing
Apply for this role →Rose International seeks a Senior SRAM Custom IC Layout Design Engineer in Santa Clara, CA, onsite for a 12-month engagement supporting NVIDIA. The role focuses on complete custom layout of SRAM bitcell arrays, memory periphery, and related macros using advanced CMOS processes.
You will lead floorplanning, DRC/LVS checks with Cadence Virtuoso and Calibre, collaborate with circuit design and PnR teams, ensure layout quality, density, and reliability targets, and mentor junior engineers while
Also on the board Same function, level within a rung
Level
Senior
Location
Santa Clara, CA
Occupation
Computer Hardware Engineers
Industry
Semiconductor and Related Device Manufacturing
Posted
yesterday