Skip to main content
Nokia in San Jose, CA is seeking a PhD/MS level analog/mixed-signal IC designer to bring high-speed ADC/DAC and PLLs to production in CMOS FinFET tech. You will design, simulate, and verify analog circuits and collaborate with layout engineers. You will create layouts, evaluate topologies for power, area, bandwidth, and work with cross-functional teams to ensure design methodology and release flows.
Required: PhD or MS in EE with 3+ years, proficiency with Cadence Virtuoso, Spectre, Calibre, and

Also on the board Same function, level within a rung

Level

Lead

Location

San Jose, CA

Occupation

Electronics Engineers, Except Computer

Industry

Semiconductor and Related Device Manufacturing

Posted

3 days ago

Apply for this role (opens in a new tab)