celero communicationsIrvine, CA
Lead Post-Silicon DVT Engineer for High-Speed ASICs
Lead Post-Silicon DVT Engineer for High-Speed ASICs
Lead Post-Silicon DVT Engineer for High-Speed ASICs
celero communicationsIrvine, CA
yesterday
Semiconductor and Related Device ManufacturingResearch and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)Semiconductor Machinery Manufacturing
Apply for this role →Celero Communications, Inc. is seeking a Principal Design Validation & Test (DVT) Engineer in Irvine, CA to spearhead post-silicon validation for next-generation coherent DSP ASICs enabling AI and hyperscale networking. You will drive silicon characterization, enable first silicon bring-up, and build validation infrastructure while collaborating across Architecture, RTL, Firmware, Systems, and Customer Engineering. Strong leadership and a strategic validation mindset are required.
Also on the board Same function, level within a rung
Level
Lead
Location
Irvine, CA
Occupation
Computer Hardware Engineers
Industry
Semiconductor and Related Device Manufacturing
Posted
yesterday