d-Matrix is seeking a senior SerDes design engineer in Santa Clara to own transistor-level SerDes blocks through silicon bring-up. You will drive the transmit and receive datapaths, develop high-speed interface architectures, and work closely with layout, SI, and firmware teams to deliver working silicon on next-generation IO chiplets. You will model, simulate, and verify complex equalization and signaling paths, conduct budgets, and contribute to testboard design while supporting backend

Also on the board Same function, level within a rung

Level

Lead

Location

Santa Clara, CA

Occupation

Computer Hardware Engineers

Industry

Semiconductor and Related Device Manufacturing

Posted

yesterday

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