BayOne Solutions seeks a DFT Lead to drive design-for-test features across advanced silicon, coordinating with RTL, test engineers and fabrication teams in a remote, full-time role. You will implement scan, mbist, boundary scan and BISR, develop DFT IP, and lead post-silicon debug efforts with limited mentorship. Requires 8–10 years in electrical/computer engineering, strong JTAG, ATPG, and experience with Tessent, Xcelium, Genus and TempPrimetime.

Also on the board Same function, level within a rung

Level

Lead

Location

New York, NY

Occupation

Electronics Engineers, Except Computer

Industry

Semiconductor and Related Device Manufacturing

Posted

5 days ago

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