Staff CPU RTL Design Engineer - RISC-V Core & MMU

SiFive, Inc. is seeking a Staff RTL Design Engineer to join their team in Santa Clara, California. You will work on designing CPU cores based on RISC-V architecture, contributing to cutting-edge hardware developments. The ideal candidate should have a BS/MS in engineering, at least 3 years of design experience, and proficiency in RTL design languages like Verilog or System Verilog. SiFive offers competitive pay, incentives, and a comprehensive benefits package.