qorvo usSan Jose, CA
Principal Analog IC Design Engineer (10882)
$170,300 - $221,500 per year
Apply (opens in a new tab)Principal Analog IC Design Engineer (10882)
Principal Analog IC Design Engineer (10882)
qorvo usSan Jose, CA
today
$170,300 - $221,500 per year
Semiconductor and Related Device ManufacturingOther Electronic Component ManufacturingPrinted Circuit Assembly (Electronic Assembly) Manufacturing
Apply for this role (opens in a new tab)Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves multiple high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense. Visit www.qorvo.com to learn how our innovative team is helping connect, protect and power our planet. Qorvos fast-growing Power Management division is at the forefront of innovation in Power Loss Protection, PMICs, Motor Control, and Battery Management solutions, serving a diverse range of applications across Mobile, Consumer, IoT, and Industrial markets. We are seeking a highly skilled Analog Power Design Engineer to develop next-generation, high-performance power management solutions. In this role, you will drive architecture, design, and validation of industry-leading analog power ICs, collaborating closely with cross-functional global teams to deliver world-class products that set new benchmarks in efficiency, reliability, and performance. This is a hybrid position where the expectation is to be onsite multiple days a week at either our Richardson TX or San Jose CA office.
Responsibilities:
Lead the design and development of high-performance analog power management ICs, ensuring best-in-class efficiency, power density, and reliability. - Collaborate with system engineers to define product architecture and specifications, balancing performance, power, and cost requirements. - Select and implement optimal circuit topologies, ensuring robustness, yield, and manufacturability. - Conduct transistor-level design, simulation, and validation to meet functional and performance specifications. - Work closely with layout engineers to optimize floor planning, parasitic, and overall silicon performance. - Engage with global design teams, including colleagues in Asia, to align on development strategies and execution plans. - Partner with test and characterization engineers to define validation methodologies, troubleshoot design issues, and optimize production test strategies. - Drive technical reviews and documentation, presenting design decisions, analysis, and trade-offs to internal stakeholders.
Required Qualifications:
A minimum of a Bachelors Degree in Electrical Engineering - 12+ years of engineering experience (or an equivalent amount of education and expereince) working in the semiconductor industry - 8+ years of experience (or an equivalent amount of education and expereince) in analog and mixed-signal Integrated circuit (IC) design, with DC-DC power converter architectures and control methodologies such as voltage mode control and current mode control - Ability to communicate highly technical concepts effectively to both technical and non-technical stakeholders - Experience working in Electronic Design Automation (EDA) tools such as EMIR tools capacitive coupling tools and flows, parasitic extraction tools, floating nodes, etc. - Experience with production release of power management ICs Preferred Qualifications: - Masters or PHD in Electrical Engineering - Experience with Cadence Virtuoso, Simplis, and ADS - Hands-on lab experience supporting high frequency switching power supplies in the semiconductor power management industry Competitive base salary commensurate with experience: $170,300 - $221,500, relevant for the California Bay Area (subject to change dependent on physical location) *Posted salary ranges are made in good faith. Qorvo reserves the right to adjust ranges depending on the experience/qualification of the se ected candidate as well as external competitivenes *
Also on the board Same function, level within a rung
Level
Manager
Salary
$170,300 - $221,500 per year
Location
San Jose, CA
Occupation
Electronics Engineers, Except Computer
Industry
Semiconductor and Related Device Manufacturing
Posted
today