Lead Memory-Centric SoC Physical Design Engineer

Samsung Semiconductor in San Jose, CA seeks an experienced physical design engineer to own memory-centric IP and full-chip implementations from RTL to GDSII. You will drive PPA convergence, timing, and floorplanning for memory controllers, NoC, and high-speed interconnects, collaborating with RTL and verification teams. The role requires strong scripting skills (Tcl/Python/Perl) and experience with AI/ML workloads, with a focus on delivering designs on time and within budget.