Senior Leader, Signal and Power Integrity/Systems Architecture (High-Speed Interconnects) - Multiple

Key Responsibilities: Define and drive end-to-end architecture for next-generation 224G and 448G PAM4 electrical interconnect systems, including SerDes, package, PCB, connector, cable, CPC, NPC, flyover, and rack-scale connectivity solutions. Lead system-level Signal Integrity (SI) and Power Integrity (PI) strategy, including channel budgeting, COM analysis, insertion loss, return loss, jitter, crosstalk, PDN design, and simulation-to-silicon correlation. Drive architecture, modeling, and optimization of high-speed link technologies spanning PHY/SerDes architectures, equalization techniques, FEC, channel operating margins, and system performance tradeoffs across bandwidth, reach, power, latency, and reliability. Partner across silicon, package, board, power, and system teams to develop and productize advanced electrical connectivity solutions leveraging advanced packaging, CPC/NPC flyover architectures, and next-generation PCB technologies. Provide technical leadership for future interconnect roadmaps, enabling scalable AI infrastructure through innovations in 224G/448G signaling, SI/PI methodologies, heterogeneous integration, and end-to-end electrical system design.