Description[Senior Manager Field Application Engineer]
Location: [Campbell CA"]Arteris connects innovation. Our technology helps the world's most visionary companies—from startups to Fortune 500 leaders—build smarter, faster semiconductors, including SoCs and chiplets. From the car you drive to AI in the cloud, Arteris connects the innovative technologies shaping tomorrow. What You'll Do as a Senior Manager Field Application Engineer at Arteris: Join our innovative team and help shape the future of semiconductor technology, including SoCs and chiplets. In this role, you will lead and develop the US Field Application Engineering team, supporting customers as they adopt Arteris interconnect and cache IP. You will work across customer engagements and internal teams to help solve complex design challenges, support account growth, and bring customer needs into product planning. Your deep understanding of digital design—from SoC architecture through implementation—along with your enthusiasm for technology, creativity, problem-solving skills, and excellent communication abilities, will make you a valued leader on our customer success team. You will help influence the architecture of primary on-chip interconnects and coherent interconnects in cutting-edge SoC designs.
Key Responsibilities: Lead and develop Field Application Engineering teams supporting non-coherent and cache-coherent interconnect and Last Level Cache IP.Provide team leadership through mentoring, resource planning, and regional pre-sales and post-sales support. Define and guide customer engagements from pre-sales and design-in through verification and production to promote account growth and reduce late-stage escalations. Deliver technical keynotes, application notes, and product demonstrations at conferences. Apply deep knowledge of NoC, AMBA (CHI, AXI, ACE, AHB), OCP, system-level deadlocks, SoC architecture, verification and emulation methodologies, and ASIC design and implementation flows. Influence product roadmaps based on customer requirements and architecture. Travel approximately 15%–25%.Collaborate with teams across the USA, EMEAI, APAC, Israel, and India.
What You Bring: At least 5 years of experience leading and developing technical teams.10–15 years of front-end digital SoC design experience, from RTL through synthesis. Strong understanding of system-on-chip architecture and semiconductor design flows. Good knowledge of AMBA protocols, as well as PCIe, CXL, die-to-die, and chip-to-chip interfaces. Team-oriented approach and excellent communication and presentation skills. Motivation to train and educate others to help solve complex problems. Proactive, customer-focused professionalism. Strong analytical and problem-solving abilities. Experience applying AI and agentic AI workflows to SoC design. This position follows a hybrid work model.
Bonus Points If You Have: Familiarity with the ARM and RISC-V ecosystems, including CPUs, interfaces, and interconnect fabrics. Understanding of cache coherency and on-chip networks. Knowledge of high-performance computing and AI hardware architectures. Knowledge of place and route, timing closure, SystemC, HDL simulation, Python, Tcl, and UNIX/Linux. Education
Requirements: BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. MS preferred. Estimated Base Salary:$180,000–$200,000 annually.
About Arteris: Arteris is a global leader in system IP for semiconductors, helping accelerate the creation of high-performance, power-efficient silicon. The world's top semiconductor and technology companies use Arteris network-on-chip (NoC) interconnect IP, system-on-chip (SoC) integration automation software, and hardware security assurance technology to improve performance and engineering productivity, reduce risk and costs, and bring complex designs to market faster. With more than 380 team members headquartered in Silicon Valley and offices around the world, we work with startups and global technology leaders to build the next generation of electronic products. We believe in people, purpose, and impact. Join us and help shape what comes next.

Also on the board Same function, level within a rung

Level

Lead

Salary

$180,000–$200,000 annually

Location

Campbell, CA

Occupation

Architectural and Engineering Managers

Industry

Semiconductor and Related Device Manufacturing

Posted

yesterday

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