Cornelis Networks, Inc. is seeking Senior ASIC Design Engineers to develop world-class SoCs for AI and HPC interconnects. You will design RTL in Verilog/System Verilog, drive timing closure with Physical Design, and work across hardware, firmware, and software teams to deliver scalable, high-performance networking solutions. Ideal candidates have 8+ years in digital ASIC design, expertise in Ethernet protocols (50G/100G/400G), and experience with RTL verification, debugging, and scripting.

Also on the board Same function, level within a rung

Level

Lead

Location

Austin, TX

Occupation

Computer Network Architects

Industry

Computer Systems Design Services

Posted

yesterday

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