Senior Static Timing Analyst - ASIC Design & ECOs

An established industry player is seeking a Static Timing Analyst to join their dynamic team. This role focuses on achieving timing closure across various levels, including block and full-chip, while managing ECO tasks and performing critical quality checks. The ideal candidate will possess a strong understanding of on-chip variations and timing analysis techniques. This position offers an exciting opportunity to contribute to cutting-edge ASIC design projects within a collaborative environment. If you're passionate about engineering and looking to make a significant impact, this role is perfect for you.