Senior Physical Design Engineer Memory-Centric SoC

Samsung Semiconductor in San Jose, CA, seeks a skilled digital physical design engineer to own memory-centric IP and full-chip floorplanning, CTS, and timing closure. You will collaborate with RTL/verification teams, develop TCL/Python flows, and contribute to AI/ML workloads while advancing PPA, power integrity, and tapeout on advanced FinFET nodes. This role offers a competitive US-wide pay range and comprehensive benefits in a collaborative, global environment.