Cisco Silicon One is seeking a Signal and Power Integrity Technical Leader in San Jose to drive ASIC packaging, SI/PI analysis, and high-speed interconnect design. You will lead a team to define rules, verify designs, and collaborate with layout and system partners to achieve optimal performance and reliability. The role requires extensive lab work, ASIC tape-out experience, and expertise in PAM4, SerDes, and 2.5D packaging.

Also on the board Same function, level within a rung

Level

Lead

Location

San Jose, CA

Occupation

Computer and Information Systems Managers

Industry

Semiconductor and Related Device Manufacturing

Posted

2 days ago

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