Advanced-Node SoC Physical Design Lead (7/5/3nm)

SK hynix memory solutions in San Jose seeks a Sr. Staff / Principal Physical Design Engineer to lead high-performance SoC physical implementation from RTL to GDS. You will work closely with front-end, DFT, power, and analog teams to optimize PPA and ensure silicon success. You will mentor junior engineers, define team methodologies, and drive tapeouts across 7nm/5nm/3nm nodes, balancing performance, power, and area in a fast-paced environment.