qualcommSanta Clara, CA
Senior ASIC DV Engineer — Tapeouts, UVM & Power
$153,200 - $229,800 per year
Apply →Senior ASIC DV Engineer — Tapeouts, UVM & Power
Senior ASIC DV Engineer — Tapeouts, UVM & Power
qualcommSanta Clara, CA
3 days ago
$153,200 - $229,800 per year
Semiconductor and Related Device ManufacturingSemiconductor Machinery ManufacturingPrinted Circuit Assembly (Electronic Assembly) Manufacturing
Apply for this role →A leading technology company in California is seeking an experienced ASIC Design Verification Engineer to oversee the verification lifecycle for digital power IPs. Please double check you have the right level of experience and qualifications by reading the full overview of this opportunity below. The ideal candidate will have at least 3 years of experience in verification roles and a Bachelor's degree or higher in related fields. xmcpwfu This position offers a competitive salary range of $153,200.00- $229,800.00 with additional benefits including a discretionary bonus program.
Also on the board Same function, level within a rung
Level
Lead
Salary
$153,200 - $229,800 per year
Location
Santa Clara, CA
Occupation
Electronics Engineers, Except Computer
Industry
Semiconductor and Related Device Manufacturing
Posted
3 days ago