Samsung Electronics America, Inc. seeks a Micro-Architect/Logic Designer to lead RTL design for coherent interconnect IP and LLC blocks. You will partner with architects to shape next-gen interconnects and drive timing, area, and power optimizations across the design flow. You will collaborate with verification, performance/power, and CAD teams, mentor junior engineers, and ensure on-schedule RTL quality meeting PPA goals in a global, dynamic environment.

Also on the board Same function, level within a rung

Level

Lead

Location

San Jose, CA

Occupation

Computer Hardware Engineers

Industry

Semiconductor and Related Device Manufacturing

Posted

yesterday

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