Senior Staff ASIC Design Engineer - RTL & Tape-out Lead

Credo in California is seeking a Senior Staff ASIC Design Engineer to own front-end RTL design, verification, and tape-outs. You will collaborate with PD, DFT, STA, and integration teams to ensure successful tape-outs and drive chip bring-up across system teams. The role demands 10+ years in ASIC design, strong Verilog/SystemVerilog RTL skills, and experience with high-speed Serdes and Ethernet. Competitive salary, bonus, equity, and comprehensive benefits are offered.