VLSI Worlds in Folsom, CA is seeking a Senior Physical Design Engineer for ASIC/SoC projects. You will lead block-level physical design from RTL to GDSII, ensuring timing, power, and area targets are met on advanced nodes. The role requires 10+ years of relevant experience and hands-on Fusion Compiler expertise. You will collaborate with RTL, EDA, and tape-out teams to deliver silicon on schedule.

Also on the board Same function, level within a rung

Level

Lead

Location

Brooklyn, NY

Occupation

Computer Hardware Engineers

Industry

Semiconductor and Related Device Manufacturing

Posted

6 days ago

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