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Job Title
Responsibilities:
  • Manage the physical implementation of low power systems-on-a-chip, starting from RTL to tape out quality databases
  • Lead physical design flow including synthesis, LEC, timing, IR drop, formal, PNR, and ECOManage outsource external design services companies as needed by project schedules
  • Currently based on Cadence tools
Requirements: Track record of leading physical design on multiple projects Proficient in scripting and automationBS or MS (preferred) degree in EE with 10+ years of relevant physical design experience
Nice to Have:
  • Significant experience with low power design.
  • Familiar with creating UPF and/or CPF and leveraging them throughout the design flow
  • Experience with Cadence Foundation Flow
Location: Irvine, California, USACampbell (Silicon Valley), California, USA

Also on the board Same function, level within a rung

Level

Lead

Location

Campbell, CA

Occupation

Electronics Engineers, Except Computer

Industry

Other Electronic Component Manufacturing

Posted

yesterday

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