Senior ASIC Frontend & Backend Engineer: DFT/STA/UPF Expert

CoAsia SEMI in the United States seeks an experienced backend IC design engineer to perform synthesis/DFT/STA/UPF cleanup and clock analysis. The role involves UPF clock analysis, formation of test-related vectors, and back-end flows including APR/PV, STA and UPF. We prefer candidates with 3–10 years in a design house, degrees in electronic engineering, and willingness to travel. English and Chinese language skills are valued, and scripting with Shell/Perl/Tcl/Python is a plus.