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Overview: In this role you will help design and deploy high-performance FPGA/ASIC solutions for low-latency trading. You’ll work with a global, cross-functional team to transform market data in RTL and build scalable hardware blocks that power cutting-edge accelerators. The work blends deep RTL design with SystemVerilog, FPGA internals, and ASIC primitives to address fast, data-driven decisions. A strong team culture and continuous learning drive this opportunity. Compensation / Benefits discretionary performance-based bonuses medical, dental, vision basic life insurance retirement savings plans sick leave and parental leave 20 vacation days and 10 paid holidays (US)
Responsibilities: Collaborate with cross-functional teams to develop and deploy custom FPGA/ASIC solutions for trading applications Investigate new technologies and tools to improve the hardware stack Contribute to a nimble hardware development tech stack
Key requirements: Professional experience (2+ years) in RTL design for FPGA or ASIC Expert SystemVerilog development skills with thorough understanding of the language Expert on low level FPGA or ASIC architectures Skilled in network communications, processing pipelines, and/or machine learning Working knowledge of Python and/or C++ Comfortable in a Linux environment Strong verification experience Familiarity with AMD Vivado is a plus Bachelor in Electrical Engineering Brilliant design, optimization, debugging and problem solving skills Collaborative, cross-functional teamwork Strong communication abilities SystemVerilog RTL design for FPGA/ASIC FPGA/ASIC architectures

Also on the board Same function, level within a rung

Level

Lead

Location

Brooklyn, NY

Occupation

Computer Hardware Engineers

Industry

Electronic Computer Manufacturing

Posted

today

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