Physical Design Engineer

Responsibilities: Execute block-level physical design implementation from floorplan to tape-out. Develop and optimize floorplans, macro placement, and power-aware design methodologies. Perform placement optimization to achieve timing, power, area, and congestion targets. Drive Clock Tree Synthesis (CTS), routing, and ECO implementation activities. Support timing analysis, timing closure, and signoff readiness. Optimize design utilization, congestion, and routability across implementation stages. Perform DFM-related fixes and support signoff closure requirements. Collaborate with STA, DFT, and RTL teams to resolve implementation issues. Support tape-out activities and ensure design quality requirements are met. Develop automation scripts using TCL, Perl, and Python to improve design productivity.

Required Skills: Strong understanding of ASIC physical design and implementation flow. Hands-on experience with Synopsys Fusion Compiler. Experience in floorplanning, placement, CTS, routing, and ECO implementation. Knowledge of timing analysis fundamentals and timing closure methodologies. Understanding of congestion management, utilization optimization, and routing concepts. Familiarity with LEF/DEF, Liberty, Verilog, and standard physical design file formats. Basic understanding of IR Drop, EM analysis, and Physical Verification flows. Strong scripting skills in TCL, Perl, and/or Python. Excellent debugging, problem-solving, and teamwork skills.